This invention relates to semiconductor devices such as Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. More particularly, it is concerned with Flash EEPROM devices comprising memory cells capable of operating at low voltages and being manufactured using conventional Complementary Metal-Oxide Semiconductor (CMOS) processes.
Application Specific Integrated Circuits (ASIC) lie at the heart of most electrical systems and devices. An ASIC contains the specific functionality of the device or system on a single Integrated Circuit (IC) or Chip. Complementary Metal-Oxide Semiconductor (CMOS) process are used in the fabrication of ASICs and the manufacture of various discrete IC devices used in electrical systems and products. In many instances, when power is first applied to an electrical system or device, the existing ASICs and/or CMOS ICs within these devices or systems may require reconfiguration or programming. Microprocessor based systems are a good example of applications requiring programming and initialization when power is first applied to the device.
Electrically Erasable Programmable Read-Only Memory (EEPROM) devices provide a means for storing reconfiguration or programming information within an electrical system or device and are comprised of an array of memory cells. Each memory cell within the EEPROM device stores a single information bit in the form of electrical charge. EEPROM memory cells may be integrated within an ASIC device or used as a discrete EEPROM device that connects to several other ICs requiring programming or reconfiguration. The EEPROM must retain stored information or code even when the system has been tuned off. For this reason they are referred to as Non Volatile Memory (NVM). The EEPROM also provides the flexibility of being electrically erasable and re-programmable, allowing programming upgrades without the need for removing the EEPROM device from the system.
Many conventional CMOS processes only require a single layer of polysilicon during fabrication. However, memory devices such as EEPROMs mostly require multiple layers of polysilicon which require several additional steps during the fabrication process. These additional steps result in increased fabrication costs, lower yields and longer processing times. Memory architectures with single polysilicon layers and requiring no process changes or additions to a baseline deep sub-micron CMOS process greatly simplify the fabrication process of CMOS devices with integrated EEPROM cells.
Single polysilicon EEPROM devices have been developed which enable device fabrication using conventional CMOS processes. However, reliability issues during memory device programming, reading and erasing operations are of concern. Subsequent program, read or erase operations on a selected memory cell or cells may cause unselected memory cells with stored electrical charge to unwantingly discharge their stored electrical charge. Alternatively, unselected memory cells with no stored electrical charge may become electrically charged. As a result of these operations, disturbance mechanisms such as program disturb, gate program, and gate erase, may affect data integrity. Consequently, the architecture of the memory cell within a given single polysilicon EEPROM device must ensure reliability, by reducing these disturbance mechanisms during device program, read or erase operations.
Some single polysilicon EEPROM devices require relatively high voltages for reliable memory cell programming or erasing. High voltage program and erase signals introduce the need for memory cells with oxide insulation regions with increased thickness and external power supply bias voltages capable of supplying sufficient programming and erase currents. The increase in the oxide insulation region thickness consumes additional die area, while the use of external power supply bias voltages introduces additional external circuitry, complexity in and power consumption. Therefore, it is desirable to fabricate a charge-transfer voltage pump device within the EEPROM device (on chip), wherein the charge-transfer pump device generates the necessary program and erase voltages. However, there is a limit to the current that can be supplied to the EEPROM memory cells by the on chip charge-transfer voltage pump, and insufficient xe2x80x9cprogrammingxe2x80x9d and xe2x80x9cerasexe2x80x9d current will decrease the program/erase window of the memory cells for storing charge or significantly increase the required program and erase times.
Accordingly, there is a need for single polysilicon EEPROM memory devices that operate at low erase and program voltages and currents. Furthermore, it is desirable that the memory cells do not suffer from various disturbances during the program, read and erase operations.
The present invention relates to single layer polysilicon memory devices, which may be fabricated using CMOS processes. In one aspect this invention relates to an EEPROM memory cell comprising a transistor device and capacitive device. The transistor device is formed on a first conductivity type semiconductor substrate wherein the transistor comprises an electrically floating gate structure, a source region within a graded diffusion region, and a drain region.
The capacitive device is formed on a second conductivity type semiconductor substrate and comprises a first and second injector region of third conductivity type, a channel region of second conductivity type separating the first and second injector regions, and a first electrically floating structure disposed above the channel region. A first edge portion of said floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of said second injector region. A control gate region of fourth conductivity type is located within the second conductivity type semiconductor substrate and the gate structure and said first floating structure are electrically connected together. The EEPROM memory cell comprising the transistor device and first capacitive device is capable of receiving bias voltages for electrically programming, electrically erasing and electrically reading the memory cell.
In another aspect of the present invention an EEPROM memory cell comprises a transistor device, a first capacitive device and second capacitive device. The transistor device is formed on a first conductivity type semiconductor substrate and comprises an electrically floating gate structure, a source region of second conductivity type either within or not within a graded diffusion region and a drain region of second conductivity type.
The first capacitive device is formed on a second semiconductor substrate of second conductivity type and comprises first and second injector regions of third conductivity type, wherein a first channel region of second conductivity type separates the first and second injector regions. A first electrically floating structure is disposed above the first channel region, wherein a first edge portion of the first floating structure overlaps a portion of the first injector region and a second edge portion of the first floating structure overlaps a portion of said second injector region. A first control gate region of fourth conductivity type is located within the second semiconductor substrate.
The second capacitive device is formed on a third semiconductor substrate region of second conductivity type, wherein the second capacitive device comprises a third and fourth injector regions of third conductivity type, a second channel region of the second conductivity type separating the third and fourth injector regions, and a second electrically floating structure disposed above the second channel region. A first edge portion of the second floating structure overlaps a portion of the third injector region and a second edge portion of the second structure overlaps a portion of the fourth injector region, and a second control gate region of fourth conductivity type is located within the third semiconductor substrate. The gate structure and the first and second structures are electrically connected together.
The EEPROM memory cell comprising the transistor device, first capacitive device and second capacitive device is capable of receiving bias voltages for electrically programming, electrically erasing and electrically reading the memory cell.
It will also be appreciated that in different aspects of the present invention, EEPROM memory cells comprising a transistor device, first capacitive device or first and second capacitive device may incorporate different structural variations.